April 3, 2000
The DSP – Mixed Signal Companion Dating Game

By Phil Welsh, DataPath Systems

As electronics move from an EDP-driven market to a communications-driven market, digital signal processing (DSP) is moving from strength to strength, in terms of both the silicon engines and the key algorithms implemented in digital hardware and software. Many major semiconductor companies now use these processing engines as both the technology drivers for and the basis of their dominant revenue product lines.
 
Degradation of the signals to be processed (SNR)—at the front end by non-optimum mixed signal front ends, chokes the power of the DSP engines and techniques to far less than optimum. Once this power is lost, sometimes irrevocably from a systems perspective, the DSP has an uphill battle in solving the problem at hand.

Major considerations at the mixed signal front-end choke points, particularly in communication channels, include:

Noise floor and bandwidth of the active, in particular, front-end circuits used (e.g., gain/attenuation)
Quantization errors in the analog-to-digital converter (ADC) channel (ADC resolution, sampling clock, channel bandwidth)
Linearity of digitized signal
Appropriate selection of analog anti-aliasing filters
Also, the need for excellent rejection of system-generated noise is a major consideration when dealing with the switching-speed current and voltage transients associated with very powerful, deep-submicron DSP engines and the pipelines that feed these engines.

The digital filtering techniques, advanced detectors, and decoders in conjunction with interpolating and decimating the target samples certainly come in to their own after the front end, but for really high-performance systems, world-class DSPs need to be matched with world-class mixed signal circuits and system design.

A case in point is asymmetric digital subscriber line modems. There are some very powerful DSP engines, both programmable and hardware dedicated, available from semiconductor vendors. DSL algorithms are being increasingly optimized to take advantage of the numerous transmit-and-receive options of the discrete multitone modulation envelopes to adjust to line performance.
But, and this is a typical example in optimal DSP design issues, the current range of mixed signal/analog front-end LSI and VLSI goes from an effective number of bits (ENOB)—from eight to 14 over the signal bandwidth and from a noise floor of minus 150dBm/Hz (almost at the copper line level)—to only minus 140dBm/Hz—well over an order of magnitude difference.
No wonder service providers and major OEM PC suppliers are wondering why their modem solutions are being "capped" in terms of line length and performance to arbitrary lengths of 12,000 feet or so. This is not because of a lack of MOPS in the DSP CPE subscriber engines. These limiting performances are a reflection of the CPE modems mixed signal solution being non-optimum.

So, next time you see that massive GFLOP announcement with the "deepest submicron process available," think to yourself 'this is great,' but how will I match up the mixed signal element to harness its true power?

Expect to see increased designer interest and awareness in wideband, high-performance, low-noise, mixed signal VLSI solutions, both as application-specific products and also as functional specific products, i.e., flexible ADCs/DACs with PGA and DSP interfaces.

If DSP circuits are the future, they'd better make sure they have a best-in-class mixed signal date for the dance. Otherwise, they will be sitting this one out.
 

Phil Welsh is director of marketing and sales for DataPath Systems, a provider of high-performance mixed signal solutions for the communications market.
 

Copyright © 2000 Cahners Business Information, A Division of Reed Elsevier, Inc.