Reference of PCDSP6 peripheral registers

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and provides a detailed description of registers of the Hardware Abstraction Layer (HAL) of the PCDSP6 Board Support Library (BSL).

List of devices that provide registers

Registers realized by	Description	Chapter
CPLD (has a Flash-based configuration memory)	The realized registers can be accessed immediately after power-on-reset.	A.
FPGA (has a RAM-based configuration memory)	The realized registers can be accessed only after downloading of the default FPGA program.	B.
On-board chips (accessed via FPGA and/or CPLD)	Usually, the realized registers can be accessed only after downloading of the default FPGA program.	C.

A. CPLD-realized peripherals

This chapter provides detailed list of the CPLD-realized registers and their bit-fields as well as the list of the symbolic values that can be used to set/get the values of the bit-fields.

List of peripherals

Name	Description	Include file	Section
AOUT	CPLD-realized Analog Output Control	bsl_aouthal.h	A.1.
BBAIO	Base-band analog input/output	bsl_bbaiohal.h	A.2.
BDAC	CPLD-realized Analog Output Control	bsl_bdachal.h	A.3.
FPGA	CPLD-realized FPGA Control	bsl_fpgahal.h	A.4.
MISC	CPLD-realized Misc. Control/Status	bsl_mischal.h	A.5.

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A.1. Peripheral AOUT : CPLD-realized Analog Output Control

List of AOUT registers

Name	DSP address	DSPP reg.	DSPP offset	Description	Section
SWAOUT1	6000 000D	180	00 000D	Source of Base-band Analog Output 1	A.1.1.
SWAOUT2	6000 000F	180	00 000F	Source of Base-band Analog Output 2	A.1.2.

Back to the Chapter A.

A.1.1. Register SWAOUT1 : Source of Base-band Analog Output 1

List of SWAOUT1 bit-fields

Type	Field name	Bits		Default value	Description
R/W	SOURCE	1-0		0	Source

List of SWAOUT1 bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	SOURCE	1-0			Source
			BAOUT BAOUT1	0	SWAOUT1 is driven by BAOUT1
			FAOUT FAOUT1	1	SWAOUT1 is driven by FAOUT1
			NOTHING	2	SWAOUT1 is not driven

Back to the Section A.1. Peripheral AOUT

A.1.2. Register SWAOUT2 : Source of Base-band Analog Output 2

List of SWAOUT2 bit-fields

Type	Field name	Bits		Default value	Description
R/W	SOURCE	1-0		0	Source

List of SWAOUT2 bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	SOURCE	1-0			Source
			BAOUT BAOUT2	0	SWAOUT2 is driven by BAOUT2
			FAOUT FAOUT2	1	SWAOUT2 is driven by FAOUT2
			NOTHING	2	SWAOUT2 is not driven

Back to the Section A.1. Peripheral AOUT

A.2. Peripheral BBAIO : Base-band analog input/output

List of BBAIO registers

Name	DSP address	DSPP reg.	DSPP offset	Description	Section
AD1RD	6800 0000	1A0	00 0000	ADC1 16-bit data read	A.2.1.
SW1_START	6800 0000	1A0	00 0000	Send ADC1 SW Start signal	A.2.2.
AD2RD	6800 0002	1A0	00 0002	ADC2 16-bit data read	A.2.3.
SW2_START	6800 0002	1A0	00 0002	Send ADC2 SW Start signal	A.2.4.
SW12_START	6800 0004	1A0	00 0004	Send ADC1 and ADC2 Software Start signals at a time	A.2.5.
SW1_UPDATE	6800 0006	1A0	00 0006	Send DAC1 Software Update signal	A.2.6.
DA1WR	6800 0006	1A0	00 0006	DAC1 16-bit data write	A.2.7.
SW2_UPDATE	6800 0008	1A0	00 0008	Send DAC2 Software Update signal	A.2.8.
DA2WR	6800 0008	1A0	00 0008	DAC2 16-bit data write	A.2.9.
SW12_UPDATE	6800 0006	1A0	00 0006	Send DAC1 and DAC2 Software Update signal	A.2.10.

Back to the Chapter A.

A.2.1. Register AD1RD : ADC1 16-bit data read

List of AD1RD bit-fields

Type	Field name	Bits		Default value	Description
R	DATA	15-0		0x0000	ADC1 16-bit data

List of AD1RD bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R	DATA	15-0			ADC1 16-bit data
			OF(val16)	0-0xFFFF	ADC1 16-bit data

Back to the Section A.2. Peripheral BBAIO

A.2.2. Register SW1_START : Send ADC1 SW Start signal

List of SW1_START bit-fields

Type	Field name	Bits		Default value	Description
W	START	0		0	Writing a dummy data, an SW_START1 is generated

List of SW1_START bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
W	START	0			Writing a dummy data, an SW_START1 is generated
			OF(val16)	0-1	Writing a dummy data, an SW_START1 is generated

Back to the Section A.2. Peripheral BBAIO

A.2.3. Register AD2RD : ADC2 16-bit data read

List of AD2RD bit-fields

Type	Field name	Bits		Default value	Description
R	DATA	15-0		0x0000	ADC2 16-bit data

List of AD2RD bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R	DATA	15-0			ADC2 16-bit data
			OF(val16)	0-0xFFFF	ADC2 16-bit data

Back to the Section A.2. Peripheral BBAIO

A.2.4. Register SW2_START : Send ADC2 SW Start signal

List of SW2_START bit-fields

Type	Field name	Bits		Default value	Description
W	START	0		0	Writing a dummy data, an SW_START2 is generated

List of SW2_START bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
W	START	0			Writing a dummy data, an SW_START2 is generated
			OF(val16)	0-1	Writing a dummy data, an SW_START2 is generated

Back to the Section A.2. Peripheral BBAIO

A.2.5. Register SW12_START : Send ADC1 and ADC2 Software Start signals at a time

List of SW12_START bit-fields

Type	Field name	Bits		Default value	Description
W	START	0		0	Writing a dummy data, an SW_START1 and an SW_START1 are generated

List of SW12_START bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
W	START	0			Writing a dummy data, an SW_START1 and an SW_START1 are generated
			OF(val16)	0-1	Writing a dummy data, an SW_START1 and an SW_START1 are generated

Back to the Section A.2. Peripheral BBAIO

A.2.6. Register SW1_UPDATE : Send DAC1 Software Update signal

List of SW1_UPDATE bit-fields

Type	Field name	Bits		Default value	Description
R	UPDATE	0		0	Reading a dummy data, an SW_UPDATE1 is generated

List of SW1_UPDATE bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R	UPDATE	0			Reading a dummy data, an SW_UPDATE1 is generated
			OF(val16)	0-1	Reading a dummy data, an SW_UPDATE1 is generated

Back to the Section A.2. Peripheral BBAIO

A.2.7. Register DA1WR : DAC1 16-bit data write

List of DA1WR bit-fields

Type	Field name	Bits		Default value	Description
W	DATA	15-0		0x0000	DAC1 16-bit data

List of DA1WR bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
W	DATA	15-0			DAC1 16-bit data
			OF(val16)	0-0xFFFF	DAC1 16-bit data

Back to the Section A.2. Peripheral BBAIO

A.2.8. Register SW2_UPDATE : Send DAC2 Software Update signal

List of SW2_UPDATE bit-fields

Type	Field name	Bits		Default value	Description
R	UPDATE	0		0	Reading a dummy data, an SW_UPDATE2 is generated

List of SW2_UPDATE bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R	UPDATE	0			Reading a dummy data, an SW_UPDATE2 is generated
			OF(val16)	0-1	Reading a dummy data, an SW_UPDATE2 is generated

Back to the Section A.2. Peripheral BBAIO

A.2.9. Register DA2WR : DAC2 16-bit data write

List of DA2WR bit-fields

Type	Field name	Bits		Default value	Description
W	DATA	15-0		0x0000	DAC2 16-bit data

List of DA2WR bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
W	DATA	15-0			DAC2 16-bit data
			OF(val16)	0-0xFFFF	DAC2 16-bit data

Back to the Section A.2. Peripheral BBAIO

A.2.10. Register SW12_UPDATE : Send DAC1 and DAC2 Software Update signal

List of SW12_UPDATE bit-fields

Type	Field name	Bits		Default value	Description
R	UPDATE	0		0	Reading a dummy data, an SW_UPDATE1 and an SW_UPDATE2 are generated

List of SW12_UPDATE bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R	UPDATE	0			Reading a dummy data, an SW_UPDATE1 and an SW_UPDATE2 are generated
			OF(val16)	0-1	Reading a dummy data, an SW_UPDATE1 and an SW_UPDATE2 are generated

Back to the Section A.2. Peripheral BBAIO

A.3. Peripheral BDAC : CPLD-realized Analog Output Control

List of BDAC registers

Name	DSP address	DSPP reg.	DSPP offset	Description	Section
SWAOUT1	6000 000D	180	00 000D	Controls the Base-band Analog Output 1 signal	A.3.1.
SWAOUT2	6000 000F	180	00 000F	Controls the Base-band Analog Output 2 signal	A.3.2.

Back to the Chapter A.

A.3.1. Register SWAOUT1 : Controls the Base-band Analog Output 1 signal

List of SWAOUT1 bit-fields

Type	Field name	Bits	Default value	Description
R/W	DRVEN	1	0	Enables drive of signal
R/W	SOURCE	0	0	Source of the signal

List of SWAOUT1 bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	DRVEN	1			Enables drive of signal
			ENABLE ENABLED	0	SWAOUT1 can be driven by BAOUT1 or FAOUT1
			DISABLE DISABLED	1	SWAOUT1 cannot be driven
R/W	SOURCE	0			Source of the signal
			BAOUT1	0	SWAOUT1 can be driven by BAOUT1
			FAOUT1	1	SWAOUT1 can be driven by FAOUT1

Back to the Section A.3. Peripheral BDAC

A.3.2. Register SWAOUT2 : Controls the Base-band Analog Output 2 signal

List of SWAOUT2 bit-fields

Type	Field name	Bits	Default value	Description
R/W	DRVEN	1	0	Enables drive of signal
R/W	SOURCE	0	0	Source of the signal

List of SWAOUT2 bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	DRVEN	1			Enables drive of signal
			ENABLE ENABLED	0	SWAOUT2 can be driven by BAOUT2 or FAOUT2
			DISABLE DISABLED	1	SWAOUT2 cannot be driven
R/W	SOURCE	0			Source of the signal
			BAOUT2	0	SWAOUT2 can be driven by BAOUT2
			FAOUT2	1	SWAOUT2 can be driven by FAOUT2

Back to the Section A.3. Peripheral BDAC

A.4. Peripheral FPGA : CPLD-realized FPGA Control

List of FPGA registers

Name	DSP address	DSPP reg.	DSPP offset	Description	Section
PROG	6000 0006	180	00 0006	FPGA PROG_B Control	A.4.1.
INIT	6000 0007	180	00 0007	FPGA INIT_B Control	A.4.2.
CS	6000 0008	180	00 0008	FPGA CS_B Control	A.4.3.
RDWR	6000 0009	180	00 0009	FPGA RDWR_B Control	A.4.4.
DATA	6000 000A	180	00 000A	FPGA Data Port Read/Write	A.4.5.
BUSY	6000 000B	180	00 000B	FPGA Busy Status	A.4.6.
DONE	6000 000C	180	00 000C	FPGA Done Status	A.4.7.

Back to the Chapter A.

A.4.1. Register PROG : FPGA PROG_B Control

List of PROG bit-fields

Type	Field name	Bits		Default value	Description
R/W	STATE	0		0	State of PROG_B signal

List of PROG bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	STATE	0			State of PROG_B signal
			LO	0	Low level
			HI	1	High level

Back to the Section A.4. Peripheral FPGA

A.4.2. Register INIT : FPGA INIT_B Control

List of INIT bit-fields

Type	Field name	Bits		Default value	Description
R	STATE	0		0	State of INIT_B signal

List of INIT bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R	STATE	0			State of INIT_B signal
			LO ERROR CLEARING	0	Low level
			HI READY	1	High level

Back to the Section A.4. Peripheral FPGA

A.4.3. Register CS : FPGA CS_B Control

List of CS bit-fields

Type	Field name	Bits		Default value	Description
R/W	STATE	0		0	State of CS_B signal

List of CS bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	STATE	0			State of CS_B signal
			LO ACTIVE	0	Low level
			HI INACTIVE	1	High level

Back to the Section A.4. Peripheral FPGA

A.4.4. Register RDWR : FPGA RDWR_B Control

List of RDWR bit-fields

Type	Field name	Bits		Default value	Description
R/W	STATE	0		0	State of RDWR_B signal

List of RDWR bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	STATE	0			State of RDWR_B signal
			LO WRITE	0	Low level
			HI READ	1	High level

Back to the Section A.4. Peripheral FPGA

A.4.5. Register DATA : FPGA Data Port Read/Write

List of DATA bit-fields

Type	Field name	Bits		Default value	Description
R/W	VALUE	7-0		0x00	Data value

List of DATA bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	VALUE	7-0			Data value
			OF(val8)	0-0xFF	Data value

Back to the Section A.4. Peripheral FPGA

A.4.6. Register BUSY : FPGA Busy Status

List of BUSY bit-fields

Type	Field name	Bits		Default value	Description
R	STATUS	0		0	Status of Busy signal

List of BUSY bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R	STATUS	0			Status of Busy signal
			LO READY	0	Low level
			HI BUSY	1	High level

Back to the Section A.4. Peripheral FPGA

A.4.7. Register DONE : FPGA Done Status

List of DONE bit-fields

Type	Field name	Bits		Default value	Description
R	STATUS	0		0	Status of Done signal

List of DONE bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R	STATUS	0			Status of Done signal
			LO BUSY	0	Low level
			HI READY DONE	1	High level

Back to the Section A.4. Peripheral FPGA

A.5. Peripheral MISC : CPLD-realized Misc. Control/Status

List of MISC registers

Name	DSP address	DSPP reg.	DSPP offset	Description	Section
DSPID	6000 0000	180	00 0000	DSP Identification	A.5.1.
I2CDAT	6000 0001	180	00 0001	I2C Data	A.5.2.
I2COE	6000 0002	180	00 0002	I2C Output Enable	A.5.3.
I2CCLK	6000 0003	180	00 0003	I2C Serial Clock	A.5.4.
LED	6000 0004	180	00 0004	LED State Control/Status	A.5.5.
DOORBELL	6000 0005	180	00 0005	Doorbell	A.5.6.
NMICMD	6000 0010	180	00 0010	Write this register to generate NMI to DSP	A.5.7.
EI7SRC	6000 0011	180	00 0011	EXTINT7 Source Select	A.5.8.

Back to the Chapter A.

A.5.1. Register DSPID : DSP Identification

List of DSPID bit-fields

Type	Field name	Bits		Default value	Description
R	ID	4-0		0x00	Identification

List of DSPID bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R	ID	4-0			Identification
			DSP1	1	The register was read from the DSP 1
			DSP2	2	The register was read from the DSP 2

Back to the Section A.5. Peripheral MISC

A.5.2. Register I2CDAT : I2C Data

List of I2CDAT bit-fields

Type	Field name	Bits		Default value	Description
R/W	DATA	0		0	Data bit

List of I2CDAT bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	DATA	0			Data bit
			LO	0	Low level
			HI	1	High level

Back to the Section A.5. Peripheral MISC

A.5.3. Register I2COE : I2C Output Enable

List of I2COE bit-fields

Type	Field name	Bits		Default value	Description
R/W	ENABLE	0		0	Enable

List of I2COE bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	ENABLE	0			Enable
			DISABLE DISABLED	0	To disable
			ENABLE ENABLE	1	To enable

Back to the Section A.5. Peripheral MISC

A.5.4. Register I2CCLK : I2C Serial Clock

List of I2CCLK bit-fields

Type	Field name	Bits		Default value	Description
R/W	CLOCK	0		0	Clock signal

List of I2CCLK bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	CLOCK	0			Clock signal
			LO	0	Low level
			HI	1	High level

Back to the Section A.5. Peripheral MISC

A.5.5. Register LED : LED State Control/Status

List of LED bit-fields

Type	Field name	Bits		Default value	Description
R/W	STATE	0		0	LED state

List of LED bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	STATE	0			LED state
			ON	0	LED turns/is on
			OFF	1	LED turns/is off

Back to the Section A.5. Peripheral MISC

A.5.6. Register DOORBELL : Doorbell

List of DOORBELL bit-fields

Type	Field name	Bits		Default value	Description
R/W	DATA	7-0		0x00	Doorbell data value

List of DOORBELL bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	DATA	7-0			Doorbell data value
			OF(val8)	0-0xFF	Doorbell data value

Back to the Section A.5. Peripheral MISC

A.5.7. Register NMICMD : Write this register to generate NMI to DSP

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A.5.8. Register EI7SRC : EXTINT7 Source Select

List of EI7SRC bit-fields

Type	Field name	Bits		Default value	Description
R/W	SOURCE	0		0	EXTINT7 Source

List of EI7SRC bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	SOURCE	0			EXTINT7 Source
			GPINT7	0	HW source: CTx_GPINT7 generates IT
			MAILBOX	1	SW source: "mailbox write" generates IT

Back to the Section A.5. Peripheral MISC

B. FPGA-realized peripherals

This chapter provides detailed list of the FPGA-realized registers and their bit-fields as well as the list of the symbolic values that can be used to set/get the values of the bit-fields.

The listed registers are provided by the default FPGA program that has to be downloaded before the realized registers can be accessed.

List of peripherals

Name	Description	Include file	Section
UBADC	FPGA-realized Base-band Analog-to-Digital Control	bsl_ubadchal.h	B.1.
UBDAC	FPGA-realized Base-band Digital-to-Analog Control	bsl_ubdachal.h	B.2.
UDDS	FPGA-realized DDS Chip Control	bsl_uddshal.h	B.3.
UFRMR	FPGA-realized Framer Control	bsl_ufrmrhal.h	B.4.
UHADC	FPGA-realized High-speed Analog-to-Digital Control	bsl_uhadchal.h	B.5.
UINT	FPGA-realized Interrupt Control	bsl_uinthal.h	B.6.
UMISC	FPGA-realized Miscellaneous registers	bsl_umischal.h	B.7.
UMLVDSB	FPGA-realized MLVDSBUS	bsl_umlvdsbhal.h	B.8.
USBUS	FPGA-realized Syncbus	bsl_usbushal.h	B.9.

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B.1. Peripheral UBADC : FPGA-realized Base-band Analog-to-Digital Control

List of UBADC registers

Name	DSP address	DSPP reg.	DSPP offset	Description	Section
FLT1CFG	6000 400B	180	00 400B	ADC1 Filter Configuration	B.1.1.
FLT2CFG	6000 400C	180	00 400C	ADC2 Filter Configuration	B.1.2.
CONV1SEL	6000 401C	180	00 401C	ADC1 Conversation Start Select	B.1.3.
CONV2SEL	6000 401D	180	00 401D	ADC2 Conversation Start Select	B.1.4.
MODE1SEL	6000 4020	180	00 4020	ADC1 Mode Select	B.1.5.
MODE2SEL	6000 4021	180	00 4021	ADC2 Mode Select	B.1.6.

Back to the Chapter B.

B.1.1. Register FLT1CFG : ADC1 Filter Configuration

List of FLT1CFG bit-fields

Type	Field name	Bits		Default value	Description
R/W	CLKDIV	7-0		0x00	Clock Division to define cutoff freq.

List of FLT1CFG bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	CLKDIV	7-0			Clock Division to define cutoff freq.
			125_KHZ	0	Cutoff freq. = 125 kHz
			62_5_KHZ	1	Cutoff freq. = 62.5 kHz
			31_25_KHZ	2	Cutoff freq. = 31.25 kHz
			25_KHZ	4	Cutoff freq. = 25 kHz

Back to the Section B.1. Peripheral UBADC

B.1.2. Register FLT2CFG : ADC2 Filter Configuration

List of FLT2CFG bit-fields

Type	Field name	Bits		Default value	Description
R/W	CLKDIV	7-0		0x00	Clock Division to define cutoff freq.

List of FLT2CFG bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	CLKDIV	7-0			Clock Division to define cutoff freq.
			125_KHZ	0	Cutoff freq. = 125 kHz
			62_5_KHZ	1	Cutoff freq. = 62.5 kHz
			31_25_KHZ	2	Cutoff freq. = 31.25 kHz
			25_KHZ	4	Cutoff freq. = 25 kHz

Back to the Section B.1. Peripheral UBADC

B.1.3. Register CONV1SEL : ADC1 Conversation Start Select

List of CONV1SEL bit-fields

Type	Field name	Bits		Default value	Description
R/W	SOURCE	3-0		0x0	Source of the ADC1 Conversion Start signal

List of CONV1SEL bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	SOURCE	3-0			Source of the ADC1 Conversion Start signal
			DSP1_SW_START1	0	DSP1_SW_START1 command
			DSP1_SW_START2	1	DSP1_SW_START2 command
			DSP2_SW_START1	2	DSP2_SW_START1 command
			DSP2_SW_START2	3	DSP2_SW_START2 command
			RBMLVDSBUS0	4	RBMLVDSBUS0 signal
			RBMLVDSBUS1	5	RBMLVDSBUS1 signal
			SYNCBUS0	6	SYNCBUS0 signal
			SYNCBUS1	7	SYNCBUS1 signal
			SYNCBUS2	8	SYNCBUS2 signal
			DSP1_TOUT0	9	DSP1_TOUT0 signal
			DSP1_TOUT1	10	DSP1_TOUT1 signal
			DSP1_TOUT2	11	DSP1_TOUT2 signal
			DSP2_TOUT0	12	DSP2_TOUT0 signal
			DSP2_TOUT1	13	DSP2_TOUT1 signal
			DSP2_TOUT2	14	DSP2_TOUT2 signal
			DDS_OUT	15	DDS Out signal

Back to the Section B.1. Peripheral UBADC

B.1.4. Register CONV2SEL : ADC2 Conversation Start Select

List of CONV2SEL bit-fields

Type	Field name	Bits		Default value	Description
R/W	SOURCE	3-0		0x0	Source of the ADC2 Conversion Start signal

List of CONV2SEL bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	SOURCE	3-0			Source of the ADC2 Conversion Start signal
			DSP1_SW_START1	0	DSP1_SW_START1 command
			DSP1_SW_START2	1	DSP1_SW_START2 command
			DSP2_SW_START1	2	DSP2_SW_START1 command
			DSP2_SW_START2	3	DSP2_SW_START2 command
			RBMLVDSBUS0	4	RBMLVDSBUS0 signal
			RBMLVDSBUS1	5	RBMLVDSBUS1 signal
			SYNCBUS0	6	SYNCBUS0 signal
			SYNCBUS1	7	SYNCBUS1 signal
			SYNCBUS2	8	SYNCBUS2 signal
			DSP1_TOUT0	9	DSP1_TOUT0 signal
			DSP1_TOUT1	10	DSP1_TOUT1 signal
			DSP1_TOUT2	11	DSP1_TOUT2 signal
			DSP2_TOUT0	12	DSP2_TOUT0 signal
			DSP2_TOUT1	13	DSP2_TOUT1 signal
			DSP2_TOUT2	14	DSP2_TOUT2 signal
			DDS_OUT	15	DDS Out signal

Back to the Section B.1. Peripheral UBADC

B.1.5. Register MODE1SEL : ADC1 Mode Select

List of MODE1SEL bit-fields

Type	Field name	Bits		Default value	Description
R/W	MODE	3-0		0x0	ADC1 Mode Select

List of MODE1SEL bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	MODE	3-0			ADC1 Mode Select
			NO_GAIN_FILT	0	Gain is Off and Filter is Off
			GAIN_ONLY	1	Gain is On and Filter is Off
			GAIN_FILT_ON	2	Gain is On and Filter is On

Back to the Section B.1. Peripheral UBADC

B.1.6. Register MODE2SEL : ADC2 Mode Select

List of MODE2SEL bit-fields

Type	Field name	Bits		Default value	Description
R/W	MODE	3-0		0x0	ADC2 Mode Select

List of MODE2SEL bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	MODE	3-0			ADC2 Mode Select
			NO_GAIN_FILT	0	Gain is Off and Filter is Off
			GAIN_ONLY	1	Gain is On and Filter is Off
			GAIN_FILT_ON	2	Gain is On and Filter is On

Back to the Section B.1. Peripheral UBADC

B.2. Peripheral UBDAC : FPGA-realized Base-band Digital-to-Analog Control

List of UBDAC registers

Name	DSP address	DSPP reg.	DSPP offset	Description	Section
SRC1SEL	6000 4000	180	00 4000	DAC1 Source Select	B.2.1.
SRC2SEL	6000 4001	180	00 4001	DAC2 Source Select	B.2.2.
FLT1CFG	6000 400D	180	00 400D	DAC1 Filter Configuration	B.2.3.
FLT2CFG	6000 400E	180	00 400E	DAC2 Filter Configuration	B.2.4.
UPD1SEL	6000 4028	180	00 4028	DAC1 Update Source Select	B.2.5.
UPD2SEL	6000 4029	180	00 4029	DAC2 Update Source Select	B.2.6.

Back to the Chapter B.

B.2.1. Register SRC1SEL : DAC1 Source Select

List of SRC1SEL bit-fields

Type	Field name	Bits		Default value	Description
R/W	SOURCE	0		0	DAC1 Source Select

List of SRC1SEL bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	SOURCE	0			DAC1 Source Select
			DSP1	0	DSP1 can drive the DAC1
			DSP2	1	DSP2 can drive the DAC1

Back to the Section B.2. Peripheral UBDAC

B.2.2. Register SRC2SEL : DAC2 Source Select

List of SRC2SEL bit-fields

Type	Field name	Bits		Default value	Description
R/W	SOURCE	0		0	DAC2 Source Select

List of SRC2SEL bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	SOURCE	0			DAC2 Source Select
			DSP1	0	DSP1 can drive the DAC2
			DSP2	1	DSP2 can drive the DAC2

Back to the Section B.2. Peripheral UBDAC

B.2.3. Register FLT1CFG : DAC1 Filter Configuration

List of FLT1CFG bit-fields

Type	Field name	Bits		Default value	Description
R/W	CLKDIV	7-0		0x00	Clock Division to define cutoff freq.

List of FLT1CFG bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	CLKDIV	7-0			Clock Division to define cutoff freq.
			125_KHZ	0	Cutoff freq. = 125 kHz
			62_5_KHZ	1	Cutoff freq. = 62.5 kHz
			31_25_KHZ	2	Cutoff freq. = 31.25 kHz
			25_KHZ	4	Cutoff freq. = 25 kHz

Back to the Section B.2. Peripheral UBDAC

B.2.4. Register FLT2CFG : DAC2 Filter Configuration

List of FLT2CFG bit-fields

Type	Field name	Bits		Default value	Description
R/W	CLKDIV	7-0		0x00	Clock Division to define cutoff freq.

List of FLT2CFG bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	CLKDIV	7-0			Clock Division to define cutoff freq.
			125_KHZ	0	Cutoff freq. = 125 kHz
			62_5_KHZ	1	Cutoff freq. = 62.5 kHz
			31_25_KHZ	2	Cutoff freq. = 31.25 kHz
			25_KHZ	4	Cutoff freq. = 25 kHz

Back to the Section B.2. Peripheral UBDAC

B.2.5. Register UPD1SEL : DAC1 Update Source Select

List of UPD1SEL bit-fields

Type	Field name	Bits		Default value	Description
R/W	SOURCE	3-0		0x0	Update Source

List of UPD1SEL bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	SOURCE	3-0			Update Source
			DSP1_SW_UPDATE1	0	DSP1 SW_UPDATE1 command
			DSP1_SW_UPDATE2	1	DSP1 SW_UPDATE2 command
			DSP2_SW_UPDATE1	2	DSP2 SW_UPDATE1 command
			DSP2_SW_UPDATE2	3	DSP2 SW_UPDATE2 command
			RBMLVDSBUS0	4	RBMLVDSBUS0 signal
			RBMLVDSBUS1	5	RBMLVDSBUS1 signal
			SYNCBUS0	6	SYNCBUS0 signal
			SYNCBUS1	7	SYNCBUS1 signal
			SYNCBUS2	8	SYNCBUS2 signal
			DSP1_TOUT0	9	DSP1_TOUT0 signal
			DSP1_TOUT1	10	DSP1_TOUT1 signal
			DSP1_TOUT2	11	DSP1_TOUT2 signal
			DSP2_TOUT0	12	DSP2_TOUT0 signal
			DSP2_TOUT1	13	DSP2_TOUT1 signal
			DSP2_TOUT2	14	DSP2_TOUT2 signal
			DDS_OUT	15	DDS Out signal

Back to the Section B.2. Peripheral UBDAC

B.2.6. Register UPD2SEL : DAC2 Update Source Select

List of UPD2SEL bit-fields

Type	Field name	Bits		Default value	Description
R/W	SOURCE	3-0		0x0	Update Source

List of UPD2SEL bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	SOURCE	3-0			Update Source
			DSP1_SW_UPDATE1	0	DSP1 SW_UPDATE1 command
			DSP1_SW_UPDATE2	1	DSP1 SW_UPDATE2 command
			DSP2_SW_UPDATE1	2	DSP2 SW_UPDATE1 command
			DSP2_SW_UPDATE2	3	DSP2 SW_UPDATE2 command
			RBMLVDSBUS0	4	RBMLVDSBUS0 signal
			RBMLVDSBUS1	5	RBMLVDSBUS1 signal
			SYNCBUS0	6	SYNCBUS0 signal
			SYNCBUS1	7	SYNCBUS1 signal
			SYNCBUS2	8	SYNCBUS2 signal
			DSP1_TOUT0	9	DSP1_TOUT0 signal
			DSP1_TOUT1	10	DSP1_TOUT1 signal
			DSP1_TOUT2	11	DSP1_TOUT2 signal
			DSP2_TOUT0	12	DSP2_TOUT0 signal
			DSP2_TOUT1	13	DSP2_TOUT1 signal
			DSP2_TOUT2	14	DSP2_TOUT2 signal
			DDS_OUT	15	DDS Out signal

Back to the Section B.2. Peripheral UBDAC

B.3. Peripheral UDDS : FPGA-realized DDS Chip Control

List of UDDS registers

Name	DSP address	DSPP reg.	DSPP offset	Description	Section
SDIO	6000 4006	180	00 4006	DDSSDIO (DDS Serial Data Bus) data bit read/write	B.3.1.
SDIODRV	6000 4007	180	00 4007	DDSSDIO_DRVENH (DDS Serial Data Bus Drive Enable) enable/disable	B.3.2.
CHIPSEL	6000 4008	180	00 4008	DDSCSL (DDS Chip Select)	B.3.3.
SCLK	6000 4009	180	00 4009	DDSSCLK (DDS Serial Clock)	B.3.4.
UPDATE	6000 400A	180	00 400A	DDSUPDATE (DDS Update)	B.3.5.

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B.3.1. Register SDIO : DDSSDIO (DDS Serial Data Bus) data bit read/write

List of SDIO bit-fields

Type	Field name	Bits		Default value	Description
R/W	DATA	0		0	Data bus (wire) state

List of SDIO bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	DATA	0			Data bus (wire) state
			LO	0	Data bus lo
			HI	1	Data bus hi

Back to the Section B.3. Peripheral UDDS

B.3.2. Register SDIODRV : DDSSDIO_DRVENH (DDS Serial Data Bus Drive Enable) enable/disable

List of SDIODRV bit-fields

Type	Field name	Bits		Default value	Description
R/W	ENABLE	0		0	Enable

List of SDIODRV bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	ENABLE	0			Enable
			DISABLE BY_DDS	0	Driven by the DDS chip
			ENABLE BY_FPGA	1	Driven by the FPGA with the content of DDSSDIO register

Back to the Section B.3. Peripheral UDDS

B.3.3. Register CHIPSEL : DDSCSL (DDS Chip Select)

List of CHIPSEL bit-fields

Type	Field name	Bits		Default value	Description
R/W	STATE	0		0	Chip Select state

List of CHIPSEL bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	STATE	0			Chip Select state
			LO ACTIVE	0	CS is lo (active)
			HI INACTIVE	1	CS is hi (inactive)

Back to the Section B.3. Peripheral UDDS

B.3.4. Register SCLK : DDSSCLK (DDS Serial Clock)

List of SCLK bit-fields

Type	Field name	Bits		Default value	Description
R/W	STATE	0		0	DDSSCLK (DDS Serial Clock)

List of SCLK bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	STATE	0			DDSSCLK (DDS Serial Clock)
			LO	0	SCLK is lo
			HI	1	SCLK is hi

Back to the Section B.3. Peripheral UDDS

B.3.5. Register UPDATE : DDSUPDATE (DDS Update)

List of UPDATE bit-fields

Type	Field name	Bits		Default value	Description
R/W	STATE	0		0	DDSUPDATE (DDS Update)

List of UPDATE bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	STATE	0			DDSUPDATE (DDS Update)
			LO	0	Update input of DDS is lo
			HI	1	Update input of DDS is hi

Back to the Section B.3. Peripheral UDDS

B.4. Peripheral UFRMR : FPGA-realized Framer Control

List of UFRMR registers

Name	DSP address	DSPP reg.	DSPP offset	Description	Section
F1ASGN	6000 4002	180	00 4002	Assign the Framer1 to a DSP	B.4.1.
F2ASGN	6000 4003	180	00 4003	Assign the Framer2 to a DSP	B.4.2.
TCLK1SEL	6000 4004	180	00 4004	Framer1 TCLK Clock Source Select	B.4.3.
TCLK2SEL	6000 4005	180	00 4005	Framer2 TCLK Clock Source Select	B.4.4.

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B.4.1. Register F1ASGN : Assign the Framer1 to a DSP

List of F1ASGN bit-fields

Type	Field name	Bits		Default value	Description
R/W	TO	0		0	Framer Control Source Select

List of F1ASGN bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	TO	0			Framer Control Source Select
			DSP1	0	DSP1 can control the Framer1
			DSP2	1	DSP2 can control the Framer1

Back to the Section B.4. Peripheral UFRMR

B.4.2. Register F2ASGN : Assign the Framer2 to a DSP

List of F2ASGN bit-fields

Type	Field name	Bits		Default value	Description
R/W	TO	0		0	Framer Control Source Select

List of F2ASGN bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	TO	0			Framer Control Source Select
			DSP2	0	DSP2 can control the Framer2
			DSP1	1	DSP1 can control the Framer2

Back to the Section B.4. Peripheral UFRMR

B.4.3. Register TCLK1SEL : Framer1 TCLK Clock Source Select

List of TCLK1SEL bit-fields

Type	Field name	Bits		Default value	Description
R/W	SOURCE	3-0		0x0	Source of Framer1 TCLK Clock

List of TCLK1SEL bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	SOURCE	3-0			Source of Framer1 TCLK Clock
			FRAMER1_RCLK	0	Framer1 RCLK
			LOCAL_2048_KHZ	1	Local 2048 kHz signal
			SYNCBUS0	2	SYNCBUS0 signal
			SYNCBUS1	3	SYNCBUS1 signal
			SYNCBUS2	4	SYNCBUS2 signal
			FRAMER2_RCLK	5	Framer2 RCLK

Back to the Section B.4. Peripheral UFRMR

B.4.4. Register TCLK2SEL : Framer2 TCLK Clock Source Select

List of TCLK2SEL bit-fields

Type	Field name	Bits		Default value	Description
R/W	SOURCE	3-0		0x0	Source of Framer2 TCLK Clock

List of TCLK2SEL bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	SOURCE	3-0			Source of Framer2 TCLK Clock
			FRAMER2_RCLK	0	Framer2 RCLK
			LOCAL_2048_KHZ	1	Local 2048 kHz signal
			SYNCBUS0	2	SYNCBUS0 signal
			SYNCBUS1	3	SYNCBUS1 signal
			SYNCBUS2	4	SYNCBUS2 signal
			FRAMER1_RCLK	5	Framer1 RCLK

Back to the Section B.4. Peripheral UFRMR

B.5. Peripheral UHADC : FPGA-realized High-speed Analog-to-Digital Control

List of UHADC registers

Name	DSP address	DSPP reg.	DSPP offset	Description	Section
CLKSEL	6000 4014	180	00 4014	HAD1 and HAD2 Clock Select	B.5.1.
FIFO	6000 401B	180	00 401B	HAD1 and HAD2 FIFO Status	B.5.2.

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B.5.1. Register CLKSEL : HAD1 and HAD2 Clock Select

List of CLKSEL bit-fields

Type	Field name	Bits		Default value	Description
R/W	SOURCE	3-0		0x0	HAD1 and HAD2 Clock Source

List of CLKSEL bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	SOURCE	3-0			HAD1 and HAD2 Clock Source
			DDSOUTPUT	0	DDS output signal
			RCLKIN	1	RCLKIN signal (50 MHz)
			L2048KHZ	2	2048 kHz clock signal
			DSP1_TOUT0	3	DSP1 TOUT0 signal
			DSP1_TOUT1	4	DSP1 TOUT1 signal
			DSP1_TOUT2	5	DSP1 TOUT2 signal

Back to the Section B.5. Peripheral UHADC

B.5.2. Register FIFO : HAD1 and HAD2 FIFO Status

List of FIFO bit-fields

Type	Field name	Bits	Default value	Description
R/W	EMPTY2	3	0	Status of HAD2 FIFO Empty
R/W	FULL2	2	0	Status of HAD2 FIFO Full
R/W	EMPTY1	1	0	Status of HAD1 FIFO Empty
R/W	FULL1	0	0	Status of HAD1 FIFO Full

List of FIFO bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	EMPTY2	3			Status of HAD2 FIFO Empty
			NOT_EMPTY	0	HAD2 FIFO is not Empty
			EMPTY	1	HAD2 FIFO is Empty
R/W	FULL2	2			Status of HAD2 FIFO Full
			NOT_FULL	0	HAD2 FIFO is not Full
			FULL	1	HAD2 FIFO is Full
R/W	EMPTY1	1			Status of HAD1 FIFO Empty
			NOT_EMPTY	0	HAD1 FIFO is not Empty
			EMPTY	1	HAD1 FIFO is Empty
R/W	FULL1	0			Status of HAD1 FIFO Full
			NOT_FULL	0	HAD1 FIFO is not Full
			FULL	1	HAD1 FIFO is Full

Back to the Section B.5. Peripheral UHADC

B.6. Peripheral UINT : FPGA-realized Interrupt Control

List of UINT registers

Name	DSP address	DSPP reg.	DSPP offset	Description	Section
INT4SRC	6000 4015	180	00 4015	INT4_SEL (Interrupt 4 Source Select)	B.6.1.
INT5SRC	6000 4016	180	00 4016	INT5_SEL (Interrupt 5 Source Select)	B.6.2.
INT6SRC	6000 4017	180	00 4017	INT6_SEL (Interrupt 6 Source Select)	B.6.3.
INT4SEND	6000 4018	180	00 4018	INT4_SEND (TINT4SEND Interrupt 4 Send to the other DSP)	B.6.4.
INT5SEND	6000 4019	180	00 4019	INT5_SEND (TINT5SEND Interrupt 5 Send to the other DSP)	B.6.5.
INT6SEND	6000 401A	180	00 401A	INT6_SEND (TINT6SEND Interrupt 6 Send to the other DSP)	B.6.6.

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B.6.1. Register INT4SRC : INT4_SEL (Interrupt 4 Source Select)

List of INT4SRC bit-fields

Type	Field name	Bits		Default value	Description
R/W	SOURCE	3-0		0x0	Interrupt 4 Source Select

List of INT4SRC bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	SOURCE	3-0			Interrupt 4 Source Select
			TINT4SEND	0	TINT4SEND of the other DSP chip
			RBMLVDSBUS0	1	RBMLVDSBUS0 signal
			RBMLVDSBUS1	2	RBMLVDSBUS1 signal
			SYNCBUS0	3	SYNCBUS0 signal
			SYNCBUS1	4	SYNCBUS1 signal
			SYNCBUS2	5	SYNCBUS2 signal
			AD1BUSYL AD1EOC	6	AD1BUSYL signal (End of AD1 conversion)
			AD2BUSYL AD2EOC	7	AD2BUSYL signal (End of AD2 conversion)
			NF1INTL	8	NF1INTL signal
			NF2INTL	9	NF2INTL signal
			HAD1OVERLOAD	10	HAD1OVERLOAD signal (HAD1 has over loaded)
			HAD2OVERLOAD	11	HAD2OVERLOAD signal (HAD2 has over loaded)

Back to the Section B.6. Peripheral UINT

B.6.2. Register INT5SRC : INT5_SEL (Interrupt 5 Source Select)

List of INT5SRC bit-fields

Type	Field name	Bits		Default value	Description
R/W	SOURCE	3-0		0x0	Interrupt 5 Source Select

List of INT5SRC bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	SOURCE	3-0			Interrupt 5 Source Select
			TINT5SEND	0	TINT5SEND of the other DSP chip
			RBMLVDSBUS0	1	RBMLVDSBUS0 signal
			RBMLVDSBUS1	2	RBMLVDSBUS1 signal
			SYNCBUS0	3	SYNCBUS0 signal
			SYNCBUS1	4	SYNCBUS1 signal
			SYNCBUS2	5	SYNCBUS2 signal
			AD1BUSYL AD1EOC	6	AD1BUSYL signal (End of AD1 conversion)
			AD2BUSYL AD2EOC	7	AD2BUSYL signal (End of AD2 conversion)
			NF1INTL	8	NF1INTL signal
			NF2INTL	9	NF2INTL signal
			HAD1OVERLOAD	10	HAD1OVERLOAD signal (HAD1 has over loaded)
			HAD2OVERLOAD	11	HAD2OVERLOAD signal (HAD2 has over loaded)

Back to the Section B.6. Peripheral UINT

B.6.3. Register INT6SRC : INT6_SEL (Interrupt 6 Source Select)

List of INT6SRC bit-fields

Type	Field name	Bits		Default value	Description
R/W	SOURCE	3-0		0x0	Interrupt 6 Source Select

List of INT6SRC bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	SOURCE	3-0			Interrupt 6 Source Select
			TINT6SEND	0	TINT6SEND of the other DSP chip
			RBMLVDSBUS0	1	RBMLVDSBUS0 signal
			RBMLVDSBUS1	2	RBMLVDSBUS1 signal
			SYNCBUS0	3	SYNCBUS0 signal
			SYNCBUS1	4	SYNCBUS1 signal
			SYNCBUS2	5	SYNCBUS2 signal
			AD1BUSYL AD1EOC	6	AD1BUSYL signal (End of AD1 conversion)
			AD2BUSYL AD2EOC	7	AD2BUSYL signal (End of AD2 conversion)
			NF1INTL	8	NF1INTL signal
			NF2INTL	9	NF2INTL signal
			HAD1OVERLOAD	10	HAD1OVERLOAD signal (HAD1 has over loaded)
			HAD2OVERLOAD	11	HAD2OVERLOAD signal (HAD2 has over loaded)

Back to the Section B.6. Peripheral UINT

B.6.4. Register INT4SEND : INT4_SEND (TINT4SEND Interrupt 4 Send to the other DSP)

Back to the Section B.6. Peripheral UINT

B.6.5. Register INT5SEND : INT5_SEND (TINT5SEND Interrupt 5 Send to the other DSP)

Back to the Section B.6. Peripheral UINT

B.6.6. Register INT6SEND : INT6_SEND (TINT6SEND Interrupt 6 Send to the other DSP)

Back to the Section B.6. Peripheral UINT

B.7. Peripheral UMISC : FPGA-realized Miscellaneous registers

List of UMISC registers

Name	DSP address	DSPP reg.	DSPP offset	Description	Section
DSPCLK	6000 4013	180	00 4013	Clock control of the DSP chips	B.7.1.

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B.7.1. Register DSPCLK : Clock control of the DSP chips

List of DSPCLK bit-fields

Type	Field name	Bits		Default value	Description
R/W	SOURCE	3-0		0x0	Clock source of the DSP chips

List of DSPCLK bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	SOURCE	3-0			Clock source of the DSP chips
			RBMLVDSBUS0	0	RBMLVDSBUS0 signal
			RBMLVDSBUS1	1	RBMLVDSBUS1 signal
			DDSOUTPUT	2	DDS output signal

Back to the Section B.7. Peripheral UMISC

B.8. Peripheral UMLVDSB : FPGA-realized MLVDSBUS

List of UMLVDSB registers

Name	DSP address	DSPP reg.	DSPP offset	Description	Section
DRV0EN	6000 400F	180	00 400F	MLVDSBUS0 Drive Enable	B.8.1.
DRV1EN	6000 4010	180	00 4010	MLVDSBUS1 Drive Enable	B.8.2.
SRC0SEL	6000 4011	180	00 4011	MLVDSBUS0 Source Select	B.8.3.
SRC1SEL	6000 4012	180	00 4012	MLVDSBUS1 Source Select	B.8.4.

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B.8.1. Register DRV0EN : MLVDSBUS0 Drive Enable

List of DRV0EN bit-fields

Type	Field name	Bits		Default value	Description
R/W	ENABLE	0		0	MLVDSBUS0 Drive Enable

List of DRV0EN bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	ENABLE	0			MLVDSBUS0 Drive Enable
			DISABLE	0	MLVDSBUS0 is not driven
			ENABLE	1	MLVDSBUS0 is driven

Back to the Section B.8. Peripheral UMLVDSB

B.8.2. Register DRV1EN : MLVDSBUS1 Drive Enable

List of DRV1EN bit-fields

Type	Field name	Bits		Default value	Description
R/W	ENABLE	0		0	MLVDSBUS1 Drive Enable

List of DRV1EN bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	ENABLE	0			MLVDSBUS1 Drive Enable
			DISABLE	0	MLVDSBUS1 is not driven
			ENABLE	1	MLVDSBUS1 is driven

Back to the Section B.8. Peripheral UMLVDSB

B.8.3. Register SRC0SEL : MLVDSBUS0 Source Select

List of SRC0SEL bit-fields

Type	Field name	Bits		Default value	Description
R/W	SOURCE	3-0		0x0	MLVDSBUS0 Source

List of SRC0SEL bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	SOURCE	3-0			MLVDSBUS0 Source
			DDSOUTPUT	0	DDS output signal
			RCLKIN	1	RCLKIN signal (50MHz)
			L2048KHZ	2	2048 kHz clock signal
			DSP1_TOUT0	3	DSP1 TOUT0 signal
			DSP1_TOUT1	4	DSP1 TOUT1 signal
			DSP1_TOUT2	5	DSP1 TOUT2 signal
			DSP2_TOUT0	6	DSP2 TOUT0 signal
			DSP2_TOUT1	7	DSP2 TOUT1 signal
			DSP2_TOUT2	8	DSP2 TOUT2 signal

Back to the Section B.8. Peripheral UMLVDSB

B.8.4. Register SRC1SEL : MLVDSBUS1 Source Select

List of SRC1SEL bit-fields

Type	Field name	Bits		Default value	Description
R/W	SOURCE	3-0		0x0	MLVDSBUS1 Source

List of SRC1SEL bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	SOURCE	3-0			MLVDSBUS1 Source
			DDSOUTPUT	0	DDS output signal
			RCLKIN	1	RCLKIN signal (50MHz)
			L2048KHZ	2	2048 kHz clock signal
			DSP1_TOUT0	3	DSP1 TOUT0 signal
			DSP1_TOUT1	4	DSP1 TOUT1 signal
			DSP1_TOUT2	5	DSP1 TOUT2 signal
			DSP2_TOUT0	6	DSP2 TOUT0 signal
			DSP2_TOUT1	7	DSP2 TOUT1 signal
			DSP2_TOUT2	8	DSP2 TOUT2 signal

Back to the Section B.8. Peripheral UMLVDSB

B.9. Peripheral USBUS : FPGA-realized Syncbus

List of USBUS registers

Name	DSP address	DSPP reg.	DSPP offset	Description	Section
SRC0SEL	6000 4022	180	00 4022	SYNCBUS0 Source Select	B.9.1.
SRC1SEL	6000 4023	180	00 4023	SYNCBUS1 Source Select	B.9.2.
SRC2SEL	6000 4024	180	00 4024	SYNCBUS2 Source Select	B.9.3.
DRV0EN	6000 4025	180	00 4025	SYNCBUS0 Drive Enable	B.9.4.
DRV1EN	6000 4026	180	00 4026	SYNCBUS1 Drive Enable	B.9.5.
DRV2EN	6000 4027	180	00 4027	SYNCBUS2 Drive Enable	B.9.6.

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B.9.1. Register SRC0SEL : SYNCBUS0 Source Select

List of SRC0SEL bit-fields

Type	Field name	Bits		Default value	Description
R/W	SOURCE	7-0		0x00	SYNCBUS0 Source

List of SRC0SEL bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	SOURCE	7-0			SYNCBUS0 Source
			RDDSCOMPOUT	0	RDDSCOMPOUT
			L2048KHZ	1	2048 kHz clock signal
			F1RCLK	2	Framer 1 RCLK
			F2RCLK	3	Framer 2 RCLK
			DSP1_TOUT0 T1_TIMER_OUT0	4	DSP1 TOUT0 signal
			DSP1_TOUT1 T1_TIMER_OUT1	5	DSP1 TOUT1 signal
			DSP1_TOUT2 T1_TIMER_OUT2	6	DSP1 TOUT2 signal
			DSP2_TOUT0 T2_TIMER_OUT0	7	DSP2 TOUT0 signal
			DSP2_TOUT1 T2_TIMER_OUT1	8	DSP2 TOUT1 signal
			DSP2_TOUT2 T2_TIMER_OUT2	9	DSP2 TOUT2 signal
			AD1SCCLK	10	AD1SCCLK signal
			AD2SCCLK	11	AD2SCCLK signal
			DA1SCCLK	12	DA1SCCLK signal
			DA2SCCLK	13	DA2SCCLK signal
			AD1CONVSTARTL	14	AD1CONVSTARTL signal
			AD2CONVSTARTL	15	AD2CONVSTARTL signal
			DA1LDACL	16	DA1LDACL signal
			DA2LDACL	17	DA2LDACL signal
			DSP1_GPINT4 T1_GP_INT4	18	DSP1 GPINT4 signal
			DSP1_GPINT5 T1_GP_INT5	19	DSP1 GPINT5 signal
			DSP1_GPINT6 T1_GP_INT6	20	DSP1 GPINT6 signal
			DSP2_GPINT4 T2_GP_INT4	21	DSP2 GPINT4 signal
			DSP2_GPINT5 T2_GP_INT5	22	DSP2 GPINT5 signal
			DSP2_GPINT6 T2_GP_INT6	23	DSP2 GPINT6 signal
			DSP1_GPIO8	24	DSP1 GPIO8 signal
			DSP2_GPIO8	25	DSP2 GPIO8 signal

Back to the Section B.9. Peripheral USBUS

B.9.2. Register SRC1SEL : SYNCBUS1 Source Select

List of SRC1SEL bit-fields

Type	Field name	Bits		Default value	Description
R/W	SOURCE	7-0		0x00	SYNCBUS1 Source

List of SRC1SEL bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	SOURCE	7-0			SYNCBUS1 Source
			RDDSCOMPOUT	0	RDDSCOMPOUT
			L2048KHZ	1	2048 kHz clock signal
			F1RCLK	2	Framer 1 RCLK
			F2RCLK	3	Framer 2 RCLK
			DSP1_TOUT0 T1_TIMER_OUT0	4	DSP1 TOUT0 signal
			DSP1_TOUT1 T1_TIMER_OUT1	5	DSP1 TOUT1 signal
			DSP1_TOUT2 T1_TIMER_OUT2	6	DSP1 TOUT2 signal
			DSP2_TOUT0 T2_TIMER_OUT0	7	DSP2 TOUT0 signal
			DSP2_TOUT1 T2_TIMER_OUT1	8	DSP2 TOUT1 signal
			DSP2_TOUT2 T2_TIMER_OUT2	9	DSP2 TOUT2 signal
			AD1SCCLK	10	AD1SCCLK signal
			AD2SCCLK	11	AD2SCCLK signal
			DA1SCCLK	12	DA1SCCLK signal
			DA2SCCLK	13	DA2SCCLK signal
			AD1CONVSTARTL	14	AD1CONVSTARTL signal
			AD2CONVSTARTL	15	AD2CONVSTARTL signal
			DA1LDACL	16	DA1LDACL signal
			DA2LDACL	17	DA2LDACL signal
			DSP1_GPINT4 T1_GP_INT4	18	DSP1 GPINT4 signal
			DSP1_GPINT5 T1_GP_INT5	19	DSP1 GPINT5 signal
			DSP1_GPINT6 T1_GP_INT6	20	DSP1 GPINT6 signal
			DSP2_GPINT4 T2_GP_INT4	21	DSP2 GPINT4 signal
			DSP2_GPINT5 T2_GP_INT5	22	DSP2 GPINT5 signal
			DSP2_GPINT6 T2_GP_INT6	23	DSP2 GPINT6 signal
			DSP1_GPIO8	24	DSP1 GPIO8 signal
			DSP2_GPIO8	25	DSP2 GPIO8 signal

Back to the Section B.9. Peripheral USBUS

B.9.3. Register SRC2SEL : SYNCBUS2 Source Select

List of SRC2SEL bit-fields

Type	Field name	Bits		Default value	Description
R/W	SOURCE	7-0		0x00	SYNCBUS2 Source

List of SRC2SEL bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	SOURCE	7-0			SYNCBUS2 Source
			RDDSCOMPOUT	0	RDDSCOMPOUT
			L2048KHZ	1	2048 kHz clock signal
			F1RCLK	2	Framer 1 RCLK
			F2RCLK	3	Framer 2 RCLK
			DSP1_TOUT0 T1_TIMER_OUT0	4	DSP1 TOUT0 signal
			DSP1_TOUT1 T1_TIMER_OUT1	5	DSP1 TOUT1 signal
			DSP1_TOUT2 T1_TIMER_OUT2	6	DSP1 TOUT2 signal
			DSP2_TOUT0 T2_TIMER_OUT0	7	DSP2 TOUT0 signal
			DSP2_TOUT1 T2_TIMER_OUT1	8	DSP2 TOUT1 signal
			DSP2_TOUT2 T2_TIMER_OUT2	9	DSP2 TOUT2 signal
			AD1SCCLK	10	AD1SCCLK signal
			AD2SCCLK	11	AD2SCCLK signal
			DA1SCCLK	12	DA1SCCLK signal
			DA2SCCLK	13	DA2SCCLK signal
			AD1CONVSTARTL	14	AD1CONVSTARTL signal
			AD2CONVSTARTL	15	AD2CONVSTARTL signal
			DA1LDACL	16	DA1LDACL signal
			DA2LDACL	17	DA2LDACL signal
			DSP1_GPINT4 T1_GP_INT4	18	DSP1 GPINT4 signal
			DSP1_GPINT5 T1_GP_INT5	19	DSP1 GPINT5 signal
			DSP1_GPINT6 T1_GP_INT6	20	DSP1 GPINT6 signal
			DSP2_GPINT4 T2_GP_INT4	21	DSP2 GPINT4 signal
			DSP2_GPINT5 T2_GP_INT5	22	DSP2 GPINT5 signal
			DSP2_GPINT6 T2_GP_INT6	23	DSP2 GPINT6 signal
			DSP1_GPIO8	24	DSP1 GPIO8 signal
			DSP2_GPIO8	25	DSP2 GPIO8 signal

Back to the Section B.9. Peripheral USBUS

B.9.4. Register DRV0EN : SYNCBUS0 Drive Enable

List of DRV0EN bit-fields

Type	Field name	Bits		Default value	Description
R/W	ENABLE	0		0	SYNCBUS0 Drive Enable

List of DRV0EN bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	ENABLE	0			SYNCBUS0 Drive Enable
			DISABLE	0	SYNCBUS0 is not driven
			ENABLE	1	SYNCBUS0 is driven

Back to the Section B.9. Peripheral USBUS

B.9.5. Register DRV1EN : SYNCBUS1 Drive Enable

List of DRV1EN bit-fields

Type	Field name	Bits		Default value	Description
R/W	ENABLE	0		0	SYNCBUS1 Drive Enable

List of DRV1EN bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	ENABLE	0			SYNCBUS1 Drive Enable
			DISABLE	0	SYNCBUS1 is not driven
			ENABLE	1	SYNCBUS1 is driven

Back to the Section B.9. Peripheral USBUS

B.9.6. Register DRV2EN : SYNCBUS2 Drive Enable

List of DRV2EN bit-fields

Type	Field name	Bits		Default value	Description
R/W	ENABLE	0		0	SYNCBUS2 Drive Enable

List of DRV2EN bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	ENABLE	0			SYNCBUS2 Drive Enable
			DISABLE	0	SYNCBUS2 is not driven
			ENABLE	1	SYNCBUS2 is driven

Back to the Section B.9. Peripheral USBUS

C. Peripherals realized by on-board chips

This chapter provides detailed list of the registers and their bit-fields realized by some on-board chips as well as the list of the symbolic values that can be used to set/get the values of the bit-fields.

Usually, the listed registers can be accessed via CPLD and/or via FPGA. To access the registers via FPGA, at first, the default FPGA program has to be downloaded.

List of peripherals

Name	Description	Include file	Section
DDSREG	DDS Chip's Registers	bsl_ddsreghal.h	C.1.

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C.1. Peripheral DDSREG : DDS Chip's Registers

List of DDSREG registers

Name	Offset	Description	Section
CFR1	0000	CFR1 Control Function Register 1	C.1.1.
CFR2	0001	CFR1 Control Function Register 2	C.1.2.
ASF	0002	ASF Amplitude Scale Factor Register	C.1.3.
ARR	0003	ARR Amplitude Ramp Rate Register	C.1.4.
FTW0	0004	FTW0 Frequency Tuning Word Register 0	C.1.5.
POW0	0005	POW0 Phase Offset Word Register 0	C.1.6.

Back to the Chapter C.

C.1.1. Register CFR1 : CFR1 Control Function Register 1

List of CFR1 bit-fields

Type	Field name	Bits	Default value	Description
R/W	LOADARR	26	0	Amplitude Ramp Rate Load Control Bit
R/W	OSKEN	25	0	Shape On-Off Keying Enable Bit
R/W	AUTOOSKKEY	24	0	Auto Shape On-Off Keying Enable Bit
R/W	AUTOSYNCEN	23	0	Automatic Synchronization Enable Bit
R/W	SWMANSYNEN	22	0	Software Manual Synchronization of Multiple AD9952s
R/W	AUTOCLRPA	13	0	Auto-Clear Phase Accumulator Bit
R/W	SINOUTEN	12	0	Sine/Cosine Select Bit
R/W	CLRPHSACC	10	0	Clear Phase Accumulator
R/W	SDIOINONLY	9	0	SDIO Input Only
R/W	LSBFIRST	8	0	LSB First
R/W	DIGPWRDN	7	0	Digital Power-Down Bit
R/W	COMPPWRDN	6	0	Comparator Power-Down Bit
R/W	DACPWRDN	5	0	DAC Power-Down Bit
R/W	CLKINPWRDN	4	0	Clock Input Power-Down Bit
R/W	EXTPWRDN	3	0	External Power-Down Mode
R/W	SYNCCLKOD	1	0	SYNC_CLK Out Disable

List of CFR1 bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	LOADARR	26			Amplitude Ramp Rate Load Control Bit
			TIMEOUT	0	ARR is loaded upon timeout only.
			IOUPDATE	1	ARR is loaded upon timeout or I/O UPDATE.
R/W	OSKEN	25			Shape On-Off Keying Enable Bit
			DISABLED BYPASSED	0	Shape on-off keying is bypassed
			ENABLED	1	Enabled
R/W	AUTOOSKKEY	24			Auto Shape On-Off Keying Enable Bit
			INACTIVE DISABLED	0	Disabled
			ACTIVE ENABLED	1	Enabled
R/W	AUTOSYNCEN	23			Automatic Synchronization Enable Bit
			INACTIVE	0	The automatic synchronization feature of multiple AD9952s is inactive
			ACTIVE	1	The automatic synchronization feature of multiple AD9952s is active
R/W	SWMANSYNEN	22			Software Manual Synchronization of Multiple AD9952s
			INACTIVE	0	The manual synchronization feature is inactive
			ACTIVE	1	The software controlled manual synchronization feature is executed
R/W	AUTOCLRPA	13			Auto-Clear Phase Accumulator Bit
			DISABLED	0	No auto-clear
			ENABLED	1	Auto-clear enabled
R/W	SINOUTEN	12			Sine/Cosine Select Bit
			COSINE	0	The angle-to-amplitude conversion logic employs a COSINE function
			SINE	1	The angle-to-amplitude conversion logic employs a SINE function
R/W	CLRPHSACC	10			Clear Phase Accumulator
			NORMAL	0	The phase accumulator functions as normal
			CLRDHELD	1	The phase accumulator memory elements are cleared and held clear
R/W	SDIOINONLY	9			SDIO Input Only
			DISABLED BIDIR	0	SDIO pin has bidirectional operation (2-wire serial prog mode)
			ENABLED INPUTONLY	1	SDIO is configured as an input only pin (3-wire serial prog mode)
R/W	LSBFIRST	8			LSB First
			DISABLED MSBFIRST	0	MSB first format is active
			ENABLED LSBFIRST	1	LSB first format is active
R/W	DIGPWRDN	7			Digital Power-Down Bit
			ENABLED OPERATES	0	Digital functions and clocks are active
			POWERDOWN	1	All non-IO digital functions are suspended
R/W	COMPPWRDN	6			Comparator Power-Down Bit
			ENABLED OPERATES	0	Comparator is enabled for operation
			POWERDOWN	1	Comparator is disabled
R/W	DACPWRDN	5			DAC Power-Down Bit
			ENABLED OPERATES	0	DAC is enabled for operation
			POWERDOWN	1	DAC is disabled
R/W	CLKINPWRDN	4			Clock Input Power-Down Bit
			ENABLED OPERATES	0	Clock input circuitry is enabled for operation
			POWERDOWN	1	Clock input circuitry is disabled
R/W	EXTPWRDN	3			External Power-Down Mode
			RAPIDRCVRY	0	Rapid recovery
			FULLPWRDN	1	Full power down
R/W	SYNCCLKOD	1			SYNC_CLK Out Disable
			ENABLED ACTIVE DISABLED	0	SYNC_CLK pin is active
			INACTIVE	1	SYNC_CLK pin is inactive

Back to the Section C.1. Peripheral DDSREG

C.1.2. Register CFR2 : CFR1 Control Function Register 2

List of CFR2 bit-fields

Type	Field name	Bits	Default value	Description
R/W	HSSYNC	11	0	High Speed Sync Enable Bit
R/W	HWMANSYNC	10	0	Hardware Manual Sync Enable Bit
R/W	CRYSTALOE	9	0	CRYSTAL OUT Enable Bit
R/W	REFCLKMUL	7-3	0x00	Reference Clock Multiplier Control Bits
R/W	VCORANGE	2	0	VCO Range Control Bit
R/W	CHRGPUMP	1-0	0	Charge Pump Current Control Bit

List of CFR2 bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	HSSYNC	11			High Speed Sync Enable Bit
			OFF DISABLED INACTIVE	0	High speed sync enchancment is off
			ON ENABLED ACTIVE	1	High speed sync enchancment is on
R/W	HWMANSYNC	10			Hardware Manual Sync Enable Bit
			OFF DISABLED INACTIVE	0	Hardware manual sync function is off
			ON ENABLED ACTIVE	1	Hardware manual sync function is active
R/W	CRYSTALOE	9			CRYSTAL OUT Enable Bit
			DISABLED INACTIVE	0	CRYSTAL OUT pin is inactive
			ENABLED ACTIVE	1	CRYSTAL OUT pin is active
R/W	REFCLKMUL	7-3			Reference Clock Multiplier Control Bits
			1X BYPASS	0	Bypass the clock multiplier. (1x mul)
			4X	4	4x multiplier
			5X	5	5x multiplier
			6X	6	6x multiplier
			7X	7	7x multiplier
			8X	8	8x multiplier
			9X	9	9x multiplier
			10X	10	10x multiplier
			11X	11	11x multiplier
			12X	12	12x multiplier
			13X	13	13x multiplier
			14X	14	14x multiplier
			15X	15	15x multiplier
			16X	16	16x multiplier
			17X	17	17x multiplier
			18X	18	18x multiplier
			19X	19	19x multiplier
			20X	20	20x multiplier
R/W	VCORANGE	2			VCO Range Control Bit
			UPTO250MHZ	0	VCO operates in a range of 100 MHz to 250 MHz
			UPTO400MHZ OVER250MHZ	1	VCO operates in a range of 250 MHz to 400 MHz
R/W	CHRGPUMP	1-0			Charge Pump Current Control Bit
			75UA	0	Charge pump current is 75 uA
			100UA	1	Charge pump current is 100 uA
			125UA	2	Charge pump current is 125 uA
			150UA	3	Charge pump current is 150 uA

Back to the Section C.1. Peripheral DDSREG

C.1.3. Register ASF : ASF Amplitude Scale Factor Register

List of ASF bit-fields

Type	Field name	Bits	Default value	Description
R/W	ARRS	15-14	0	Auto Ramp Rate Speed Control
R/W	ASF	13-0	0x0000	Amplitude Scale Factor Register

List of ASF bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	ARRS	15-14			Auto Ramp Rate Speed Control
			SS1	0	Auto-Scale Factor Internal Step Size is 1
			SS2	1	Auto-Scale Factor Internal Step Size is 2
			SS4	2	Auto-Scale Factor Internal Step Size is 4
			SS8	3	Auto-Scale Factor Internal Step Size is 8
R/W	ASF	13-0			Amplitude Scale Factor Register
			OF(val32)	0-0x3FFF	Amplitude Scale Factor Register

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C.1.4. Register ARR : ARR Amplitude Ramp Rate Register

List of ARR bit-fields

Type	Field name	Bits		Default value	Description
R/W	ARR	7-0		0x00	Amplitude Ramp Rate

List of ARR bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	ARR	7-0			Amplitude Ramp Rate
			OF(val32)	0-0xFF	Amplitude Ramp Rate

Back to the Section C.1. Peripheral DDSREG

C.1.5. Register FTW0 : FTW0 Frequency Tuning Word Register 0

List of FTW0 bit-fields

Type	Field name	Bits		Default value	Description
R/W	FTW	31-0		0x00000000	Frequency Tuning Word

List of FTW0 bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	FTW	31-0			Frequency Tuning Word
			OF(val32)	0-0xFFFFFFFF	Frequency Tuning Word

Back to the Section C.1. Peripheral DDSREG

C.1.6. Register POW0 : POW0 Phase Offset Word Register 0

List of POW0 bit-fields

Type	Field name	Bits		Default value	Description
R/W	POW	13-0		0x0000	Phase Offset Word

List of POW0 bit-fields' symbolical values

Type	Field name	Bits	Symbol name	Value	Description
R/W	POW	13-0			Phase Offset Word
			OF(val32)	0-0x3FFF	Phase Offset Word

Back to the Section C.1. Peripheral DDSREG