The ongoing revolution in digital communications is dramatically impacting the performance of analog-to-digital converters (ADCs) as systems designers shove the ADC closer to the antenna. Sampling at the IF of the wideband base-station receiver or digitizing multiple channels in a software radio translates into a higher dynamic range with faster conversion and better signal-to-noise ratio (SNR), as well as improved spurious-free dynamic range (SFDR). Portable cellular handsets are demanding this level of performance at lower power consumption, in addition to micro-miniature packages.

The proliferation of digital techniques in consumer, industrial, and instrumentation applications is propelling improvements across the board, starting at 8 bits and reaching all the way up to 24 bits. Consequently, ADC manufacturers are combining advances in CMOS, biCMOS, and complementary bipolar (CB) processes with innovative architectures to develop a broad portfolio of high-performance ADCs.

Communication ADCs

Responding to the communications call, high-performance data-converter suppliers have begun to release monolithic 14-bit ADCs capable of sampling at 65 Msamples/s, and offering a 75-dB signal-to-noise ratio (SNR) and an SFDR over 90 dB. Two recent introductions boasting this level of performance from 14-bit ADC chips come from Analog Devices (ADI) and Burr-Brown. While ADI has combined its high-speed complementary-bipolar process with multipass circuits to deliver the single-chip AD6644, Burr-Brown has tapped its low-cost 0.5-µm CMOS process to ready the monolithic ADS852.

According to ADI, laser trimming at the wafer level guarantees 14-bit accuracy from the 14-bit AD6644. The use of dither enhances SFDR performance to 100 dB. "This allows the ADC to start conversion at the IF to replace traditional IF and RF filters with predictable digital filters, thereby lowering the component count, as well as the cost of the receiver," states Scott Behrhorst, marketing and applications manager for ADI's Digital Radio Group. Operating from a single 5-V supply, the AD6644 includes an on-chip track-and-hold (T/H) circuit and a reference to achieve an input bandwidth in excess of 450 MHz (Fig. 1). It provides CMOS-compatible digital outputs at 65 Msamples/s. Packaged in a 52-pin thin quad flatpack (TQFP), the AD6644 typically dissipates 1.2 W. Efforts are under way to extend this speed to 100 Msamples/s, with added value.

Meanwhile, ADI also plans to implement this architecture in submicron lithography to boost the sampling rate beyond 100 Msamples/s at 12 and 14 bits. The company intends to achieve a sampling rate of several hundred MHz at 12 bits by the summer of 2000. Concurrently, it's also investigating a 16-bit, 65-Msamples/s version for radar applications.

Likewise, Burr-Brown's ADS852 utilizes a proprietary input T/H circuit design that allows the 14-bit pipelined ADC to track at Nyquist rates, without any loss in spurious response. "To maintain the integrity of the held input signal, all aspects of the design have been optimized to reduce errors resulting from clock feed-through, capacitor mismatch, and op-amp open-loop gain," says Patrick Kirk, strategic marketing manager at Burr-Brown. The op-amp open-loop gain and bandwidth were optimized for each stage in terms of the settling time and power dissipation.

To obtain an open-loop gain of about 100 dB and a unity gain bandwidth in excess of 1 GHz, a cascaded op-amp architecture was implemented in 0.5-µm CMOS. Says Kirk, "The new 14-bit, 65 Msamples/s ADS852 has been designed to give the necessary carrier-to-noise (C/N) dynamic range demanded by wideband base-station receivers. It achieves a C/N ratio of 104 dB without the use of an AGC." To ensure no missing codes at 14 bits, the ADS852 incorporates digital error correction (Fig. 2). Designed for single 5-V operation, it comes with many other bells and whistles. Some of these include a low jitter of 0.25-ps RMS, differential or single-ended inputs, and a selectable full-scale input range. Typical power consumption is 650 mW. It comes in a 48-lead TQFP.

For applications that need lower power, Burr-Brown is offering a 400-mW version, the ADS851, which samples below 65 Msamples/s. Aside from wideband communications receivers, the 40-MHz chip targets ultrasound and charge-coupled-device (CCD) imaging. The company also is sampling a 12-bit, 75-Msample/s ADS808 for those designers who need higher sampling rates, but can live with 12-bit resolution. Like the ADS852/1, the ADS808 is offered in a 48-lead TQFP package. Yet Kirk does not see the 14-bit ADCs going down to 3.3 V very soon. Instead, he foresees the integration of digital-down converters (DDCs) riding the tail end of these high-performance ADC ICs later in the year.

National Semiconductor and Texas Instruments, both major players in communications, also are keeping a close tab on ADC developments. In line with its digital-signal-processing (DSP) solutions strategy, TI is preparing high-speed ADCs with resolutions of 12 bits and higher, as well as on-chip interfaces to its DSPs. Leveraging its strength in deep-submicron CMOS, TI's goal is to develop an 18-bit, 200-Msamples/s ADC for cellular base stations by 2003. While no details on the TI products are available, it's expected that these ADCs will hit the market in the second quarter. Like Burr-Brown, TI also favors CMOS for lower power and higher integration. The company's CMOS process progression shows 0.18-µm geometries this year, with migration to 0.15 µm by the year 2000. TI expects to implement 0.09-µm effective channel lengths by 2001, moving to 0.07 µm by 2004.

On the other hand, National Semiconductor's Comlinear Division, Fort Collins, Colo., will continue to tap the benefits of submicron biCMOS to extend the performance of its 12-bit ADC chip for wideband digital receivers. In the works is a 14-bit version expected to be released sometime this quarter.

"While a 14-bit ADC seems adequate for addressing the needs of base-station receivers based on wideband CDMA standards, GSM900 receivers converting to wideband designs require even better performance," says Kurt Rentel, National's marketing director for system products. According to Rentel, wideband GSM900 designs require an extra 10 dB of dynamic range with higher SNR and improved distortion performance (Fig. 3). Toward that end, National is looking to develop a 16-bit ADC with better noise performance. However, additional details on this project were unavailable. Meanwhile, the company is readying a 14-bit ADC with rates between 5 and 8 Msamples/s for xDSL modem applications. Based on 0.5-µm CMOS, the 14-bit ADC for xDSL modems is planned for introduction in the fall.

Another key contender joining the wideband fray is Harris Semiconductor. While adequately serving narrowband receiver designs with its current line of 12- and 14-bit parts, Harris foresees a trend toward wideband receivers in base stations. "These receivers are demanding ADCs that can process large bandwidths and maintain the dynamic range," says Harris' product marketing engineer, Juan Garcia. Consequently, Harris is developing competitive, 0.6-µm CMOS, 14-bit ADCs using a multistage pipelined circuit.

High-Quality Imaging

The digital revolution also has pervaded the world of imaging and video systems. For improved quality, these applications seek higher-resolution converters with accuracy as high as 14 bits. Several vendors have readied 14-bit parts with the linearity and accuracy needed in these applications. Furthermore, they're exploiting pipelined architectures to obtain acceptable time-domain specifications for noise, bandwidth, and fast transient response.

Maxim Integrated Products' answer to these requirements includes the 2.2/1-Msamples/s, 5-V MAX1201/1205 ADCs. For those needing even higher resolution for improved gray scale, the company has readied the 16-bit, 1-Msample/s MAX1200. The 1200/1201/1205 versions come in 44-lead metric quad flatpacks (MQFPs). According to Maxim's business manager, David Bernel, "The converters' very low differential nonlinearity (DNL) error of ±0.3 LSB and self-calibration on demand provide a cost-effective alternative to expensive hybrids in demanding, high-resolution imaging applications."

Other contenders pursuing this activity include Analog Devices (ADI), Exar Corp., Linear Technology (LTC), National Semiconductor, and Signal Processing Technologies (SPT). Like Maxim, ADI has adopted a differential pipelined architecture with digital correction logic to guarantee no missing codes over the full temperature range. Indeed, ADI has extended the speed of its CMOS pipelined, 14-bit AD9240 to 10 Msamples/s, while dissipating only 285 mW. Tailored for single 5-V supply operation, it comes in a 44-pin MQFP.

In the meantime SPT, which has been pushing the performance envelope of 12-bit ADCs for CCD cameras, sensors, medical imaging, and other applications, has set its sight on 14-bit solutions. According to SPT's director of marketing, Rick Mintle, the company is developing a 14-bit, 0.5-µm biCMOS ADC chip with a 20-MHz conversion rate that includes a differential pipelined architecture with on-chip self calibration. "The extra 2 bits mean the LSB is four times smaller," explains Mintle. "So, the designer must pay attention to signal conditioning, layout, bypassing, and grounding. Also, the differential input makes external noise and common-mode noise cancel out." Like other 14-bit ADC suppliers, SPT is offering evaluation boards that should help designers better understand the device.

LTC's current solution for CCD camera, sensor, medical imaging, and other applications is the 12-bit, 10-Msamples/s pipelined LTC1420. But the company also is readying a 14-bit version with attractive INL and DNL specifications. The 250-mW, 14-bit device will provide higher resolution with linearity specifications similar to its 12-bit kin, as well as high SINAD (SNR and distortion) and SFDR. "While faster parts can sample more pixels in a single clock cycle, the higher number of bits allow more shades of gray in such applications," says Willie Rempfer, LTC's design engineering manager for data-converter products. The pipelined 14-bit part will sample within the next six months, with production to follow soon after. The 12-bit LTC1420 is available in a 28-pin shrink SOP (SSOP), while the 14-bit model will come in a 36-lead SSOP.

Improving Audio

The insatiable quest for better audio performance is forcing designers toward 24-bit ADCs with a 96-kHz output data rate and very high SNRs and SINAD. Even 192-kHz versions are on the horizon.

To support the newest standard for high-end audio systems, Asahi Kasei Microsystems (AKM) Co., a subsidiary of Japan's Asahi Chemical Industry Co. Ltd., has extended its dual-bit delta-sigma architecture to support higher output data rates with 24-bit resolution. The result is the AK5393, a 24-bit, 128X-oversampling, 2-channel stereo converter with data rates as high as 108 kHz. It also flaunts a dynamic range of 117 dB and SINAD of 105 dB. On-chip are digital low-pass and high-pass filters and an offset calibration, easing system design. To provide 128X oversampling, the analog modulator samples the input at 6.144 MHz. The converter features differential inputs to minimize the input noise (Fig. 4). Additionally, the manufacturer recommends more attention at the input section to maintain audio quality at the output. Housed in a 28-lead SOP package, the AK5393 consumes a maximum of 630 mW. A 192-kHz version is slated for the second half of this year.

Another major proponent of the delta-sigma 24-bit solution for high-end audio is Cirrus Logic's Crystal Division, which is currently focused on cutting the power consumption of its 24-bit, 96-kHz CS5396/97 by 30 to 40%. The trick is to do this without compromising the 120-dB dynamic range and the -105-dB total harmonic distortion plus noise (THDN). To obtain this performance, Crystal's designers are optimizing the digital filter and modifying the architecture to run the digital portion of the design on 3.3 V. Expected to be sampled later in this quarter, the CS5398 is pin-compatible with the - CS5396/97.

Crystal also is investigating a multibit delta-sigma architecture as it prepares to push the dynamic range of these converters to 125 dB. The company's roadmap indicates that multibit delta-sigma solutions will be ready for release to the fabs by year-end. "In using such high-performance converters, the system designer must ensure that input op amps and buffers are extremely low noise, and the layout is proper," says Tom Stein, Crystal's marketing manager for audio converters.

ADI plans to enter the market later this year. Observing increasing activity in this high-end professional sector, it's preparing a 24-bit, 96-kHz solution using 0.5- µm CMOS.

Data Acquisition

Many low-frequency applications like sensing, vibration analysis, seismic data acquisition, medical imaging, and instrumentation are seeking precision as high as 24 bits.

Two notable introductions to serve this world include LTC's LTC2400 and ADI's AD1555. Although both of these solutions use delta-sigma modulation techniques to achieve 24-bit resolution, there are many differences on-chip. While the LTC2400 is implemented in 2-µm CMOS, the AD1555 is based on biCMOS. The CMOS LTC2400 incorporates on-chip digital filtering and decimation.

The biCMOS AD1555, unlike the LTC2400, requires an accompanying FIR digital filter/decimator - the AD1556 - to realize the full potential of the ADC. On the other hand, keeping the digital filter separate results in a very high SNR of 118 dB. Additionally, the AD1555 implements continuous-time, delta-sigma operation with a switched-capacitor feedback digital-to-analog converter (DAC) to obtain a guaranteed low distortion of -116 dB. "This feature eliminates the need for an external anti-alias filter," notes Alain Query, senior applications engineer at ADI. "Also," he adds, "the external CMOS-based FIR digital filter provides optimized output data rates from 250 samples/s to 16 kilosamples/s." The AD1555 has a programmable gain amplifier (PGA), as well as a multiplexer. It consumes 80 mW, and comes in a 28-pin, plastic leadless chip carrier (PLCC). Likewise, the companion AD1556 is rated for 20 mW dissipation, and is offered in a 44-lead PLCC.

Testing such high-resolution ADCs is difficult and expensive. To simplify the task, ADI is considering the integration of a DAC to generate a high-purity signal on the same die. Furthermore, to reduce the footprint and cost, the company is checking into developing a multichannel digital filter that can handle several modulators. Meanwhile, LTC is working on adding features to the recently unwrapped LTC2400 (Electronic Design, Sept. 1, 1998, p. 68). Key enhancements include higher speed, lower noise, and the addition of a multiplexer.

Also in this race is Burr-Brown, with plans to sample a lower power version of the second-order, delta-sigma, 24-bit ADS1210/1211 by the end of the first quarter. The newest offering will include an 8-channel differential input multiplexer. Simultaneously, the company also is readying a 20-bit, 25-kHz ADS1250 with an on-chip PGA and digital filtering, as well as a DSP interface.